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| E2B0047-27-Y2 Semiconductor MSM6568A Semiconductor 160-DOT COMMON DRIVER This version: MSM6568A Nov. 1997 Previous version: Mar. 1996 GENERAL DESCRIPTION The MSM6568A is a dot matrix LCD common driver which is fabricated in CMOS technology. The MSM6568A consists of two 80-bit bidirectional shift registers, two 80-bit level shifters, and two 80-bit 4-level drivers. The MSM6568A is equipped with 160 output pins. By connecting two or more MSM6568A devices in cascade, the number of LCD outputs can be increased. The MSM6568A can drive a variety of LCD panels because the bias voltage, which determines the LCD driving voltage, can be optionally supplied from an external source. FEATURES * Logic supply voltage : 2.7 to 5.5V * LCD driving voltage : 14 to 28V * Applicable LCD duty : 1/64 to 1/256 * External bias power supply available * Package : TCP mounting with 70mm wide film (Product name : MSM6568AV-Z) Tin-plated 1/8 Semiconductor MSM6568A BLOCK DIAGRAM O1 O2 O79 O80 VDD V1R V2R V5R VEER 80-BIT 4-LEVEL DRIVER VEE DF DISPOFF 80-BIT LEVEL SHIFTER SHL CP IO1 VDDR/L VSSR/L VSS VDD 80-BIT SHIFT REGISTER IO80 80-BIT SHIFT REGISTER IO81 IO160 80-BIT LEVEL SHIFTER V1L V2L V5L VEEL 80-BIT 4-LEVEL DRIVER VDD VEE O81 O82 O159 O160 (VDDR/L stands for VDDR and VDDL, and VSSR/L for VSSR and VSSL.) 2/8 Semiconductor MSM6568A PIN CONFIGURATION (TOP VIEW) O160 (LCD output side) O1 Chip Surface 123 (LCD input side) Pin 1 2 3 4 5 6 7 8 9 10 11 Symbol V1L V2L V5L VEEL NC VDDL SHL VSSL DISPOFF CP DF Pin 12 13 14 15 16 17 18 19 20 21 22 Symbol IO160 IO81 IO80 IO1 VSSR VDDR NC VEER V5R V2R V1R 18 19 22 NC : No connection 3/8 Semiconductor MSM6568A ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Bias Voltage Input Voltage Storage Temperature Symbol VDD VLCD VI TSTG Condition Ta=25C Ta=25C, VDD - VEE Ta=25C -- Rating -0.3 to +6.5 0 to 30 -0.3 to VDD+0.3 -30 to +85 Unit V V V C * V1>V2>V5>VEE VEE RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Bias Voltage Operating Temperature Symbol VDD VLCD Top VDD - VEE -- Condition -- No load LCD being driven Range 2.7 to 5.5 14 to 28 18 to 28 -20 to +75 Unit V V V C * V1>V2>V5>VEE VEE 4/8 Semiconductor MSM6568A ELECTRICAL CHARACTERISTICS DC Characteristics (VDD=2.7 to 5.5V, Ta=-20 to +75C) Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage ON Resistance Supply Current Input Capacitance Symbol VIH *1 VIL *1 IIH IIL *1 *1 Condition -- -- VI=VDD, VDD=5.5V VI=0V, VDD=5.5V IO=-0.2mA, VDD=2.7V IO=0.2mA, VDD=2.7V VDD-VEE=25V | VN-VO |=0.25V CP=22kHz, VDD=3.0V VDD-VEE=25V, no load*5 f=1MHz *3 Min. 0.8VDD -- -- -- VDD-0.4 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- 5 Max. -- 0.2VDD 1 -1 -- 0.4 2.0 50 300 -- Unit V V mA mA V V kW mA pF VOH *2 VOL *2 RON *4 ISS IEE CI *1 Applied to CP, IO1, IO80, IO81, IO160, SHL, DF, DISPOFF *2 Applied to IO1, IO80, IO81, IO160 *3 VN=VDD to VEE, V2=1/16 (VDD - VEE), V5=15/16 (VDD - VEE) VDD=V1, VDD=4.5V, V1=V1L=V1R, V2=V2L=V2R, V5=V5L=V5R, VEE=VEEL=VEER, VDD=VDDL=VDDR *4 Applied to O1 to O160 *5 Input a "H" level signal through the IO pins every 240 clock pulses when a supply current is measured. The DF frequency is 45Hz. Switching Characteristics Parameter "H", "L" Propagation Delay Time Maximum Clock Frequency Clock Pulse Width Data Setup Time IOnAECP Data Hold Time CPAEIOn Rise Time / Fall Time of CP *1 *1 Symbol tPHL tPLH fCP tWCP tsetup thold tr(CP) tf(CP) Condition -- -- -- -- -- -- (VDD=2.7 to 5.5V, Ta=-20 to +75C, CL=15pF) Min. -- 1 63 100 100 -- Typ. -- -- -- -- -- -- Max. 3 -- -- -- -- 20 Unit ms MHz ns ns ns ns *1 IOn=IO1-IO160 5/8 Semiconductor MSM6568A tf(CP) tWCP 0.8VDD CP 0.2VDD tr(CP) 0.8VDD tsetup IO1 (IO80) IO81 (IO160) 0.8VDD 0.2VDD thold 0.8VDD 0.2VDD tPLH(tPHL) IO80 (IO1) IO160 (IO81) 0.8VDD 0.2VDD 6/8 Semiconductor MSM6568A FUNCTIONAL DESCRIPTION Pin Functional Description * IO1, IO80, IO81, IO160 Data input/output pins for the two 80-bit bidirectional shift registers. * SHL Input pin to select the shift direction of the two 80-bit bidirectional registers. Table 1 shows the relations between the SHL pin and the IO1, IO80, IO81, IO160 pins. * CP Clock pulse input pin for the two 80-bit bidirectional shift registers. Scan data shifts at the falling edge of a clock pulse. * DF Signal input pin to synchronize with AC current for LCD driving waveforms. Normally an inverted frame signal is input to this pin. * VDDL, VDDR, VSSL, VSSR Power supply pins. Normal operating conditions are VDDR=VDDL=2.7 to 5.5V, VSSR=VSSL=0V. * DISPOFF Input pin to control the O1 to O160 outputs. During input of "L" level, V1 levels are output from O1 to O160. * V1L, V1R, V2L, V2R, V5L, V5R, VEEL, VEER Bias voltage input pins for LCD driving. Voltages must be input to all these pins. * O1 to O160 4-level driver output pins corresponding to each bit of the shift registers. The V1, V2, V5, or VEE level is selected and output based on the combination of shift register data and a DF signal. Table 2 shows the relations between the scan data and the LCD driving outputs. Table 1 SHL Shift direction IO1, IO81 / IO80, IO160 O1AEO80 O81AEO160 IO1, IO81 IO80, IO160 IO80, IO160 IO1, IO81 I/O Input Output Input Output Input IO1 and IO81 are data input pins for the shift register. Data is input to these pins in synchronization with clocks and is output from IO80 and IO160 with delay by the number (80) of shift register bits in synchronization with clocks. IO80 and IO160 are data input pins for the shift register. Data is input to these pins in synchronization with clocks and is output from IO1 and IO81 with delay by the number (80) of shift register bits in synchronization with clocks. L H O80AEO1 O160AEO81 Table 2 Scan data H L LCD driving output Select levels (V1, VEE) Non-select levels (V2, V5) 7/8 Semiconductor Truth Table DF L L H H X Shift register data L H L H X DISPOFF H H H H L MSM6568A Driver output level (O1-O160) V2 VEE V5 V1 V1 X : Don't Care 8/8 |
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